Driver Circuit for Reducing the Effects of Disturbances on the Duty Cycle of a Digital Signal on a Bus Conductor

ABSTRACT

An electronic circuit contains a driver circuit ( 12 ) with an output coupled to a digital communication conductor ( 14 ), for driving changes of a potential at the digital communication conductor ( 14 ) to and from a digital signal level. The driver circuit ( 12 ) comprises a control circuit ( 120 ), to generate selection signals that select increasingly stronger drive strengths and increasingly weaker drive strengths during changes to and from the digital level respectively. A controllable current supply circuit ( 122, 124 ), has a current control input coupled to the control circuit ( 120 ) for receiving the selection signals and a current supply output coupled to the digital communication conductor ( 14 ). A detector circuit ( 126 ) has an input coupled to the digital communication conductor ( 14 ) and an output coupled to the control circuit ( 120 ), and arranged to detect whether a potential at the digital communication conductor ( 12 ) has reached a required range. The control circuit ( 120 ) stores information about the drive strength that was selected when the detector circuit ( 126 ) indicated that the range was reached during the change to the digital level, and during the change it restores the drive strength to the last stored drive strength as a first step during the change away from the digital level.

The invention relates to an electronic circuit with a digitalcommunication conductor, such as a conductor of a communication bus andto a method of driving the signal level at the communication conductor.

PCT patent application No. WO 2004/004259 describes a driver circuit fora CAN bus or a LIN bus. The CAN bus and the LIN bus are examples ofelectronic busses that are used to communicate information betweendifferent parts of a circuit. A bus comprises one or more communicationconductors that connect the different parts of the circuit.

It is desirable to be able to control the slew rate of the potential ofa bus conductor. The slew rate is the rate at which a potential on thebus conductor changes when it changes from one logic level to another.To control the slew rate WO 2004/004259 couples a plurality of driverelements in parallel to the bus conductor, for driving the potential ofthe bus conductor to a digital level. During the switch from one logiclevel to another progressively more of these driver elements areactivated. A feedback loop is used to compare the signal at the busconductor with a reference signals that has a desired slew rate and thecomparison result is used to control the time of activation of thedriver elements so as to match the signal at the bus conductor to thedesired slew rate.

Bus conductors often have to operate under hostile conditions. Externaldisturbances and unpredictable impedance effects can give rise tounpredictable signal level variations. Bus interface circuits should bedesigned to be robust for such variations. First of all, of course, thecircuits should be designed to prevent damage due to large signalvariation. Furthermore, it should be prevented as much as possible thatsignal variations lead to errors in the digital data that is obtainedfrom the bus conductors.

One of the aspects of a digital signal on a bus conductor is its dutycycle, that is, the fraction of time that the signal assumes a certainlogic level. In many bus circuits, assumptions are made about the dutycycle to detect digital information. However, the duty cycle can bedisturbed by signal variations at the transition from one logic level toanother. In particular when use is made of a number of driver elementsthat are progressively activated, the drive strength will not be largeinitially. As a result disturbances at that time can easily affect theduty cycle.

Among others, it is an object of the invention to reduce the effects ofdisturbances on the duty cycle of a digital signal on a digitalcommunication conductor like a bus conductor.

An electronic circuit and a method of controlling a potential of acommunication conductor according to the invention are set forth in theindependent claims. The drive strength, with which the communicationconductor is driven to a digital level, is increased preferably inpredetermined steps when the potential is changed to the digital level.When the potential is changed away from the digital level the drivestrength is progressively decreased, also preferably in predeterminedsteps. According to the invention a detector is used to detect when thepotential enters a predetermined range around the digital level andinformation about the drive strength at that time is stored. When thepotential is changed away from the digital level the drive strength isinitially returned substantially in one step to the level represented bythis information. Thus, if the potential reaches the range sooner thannormal due to a disturbance (i.e. with a weaker drive strength thannormal), the initial step when the potential is changed away from thedigital level provides for a lower drive strength. Thus, the effect ofthe disturbance on the duty cycle (the time interval between the timepoints where the potential reaches the interval and leaves the interval)is reduced.

In an embodiment a permanently connected resistor is used to pull thepotential away from the digital level, the progressively increasing anddecreasing driving strength driving the potential against the effect ofthis resistor. As a result of the return, substantially in one step, tothe level represented by the stored information, the counteraction ofthe effect of the resistor is reduced more at the end of the duty cycleif the duty cycle starts sooner. In another embodiment, one or moreactively switched driving element may be used instead of the resistor,or in addition to the resistor, to drive the potential away from thedigital level.

In an embodiment a plurality of switchable driving elements, which eachproduce a predetermined drive strength when active, are coupled to thecommunication conductor in parallel. In this embodiment the drivestrength is progressively increased and decreased by activating more orfewer of the driving elements. In this embodiment the stored informationpreferably represents which of the driving elements where active whenthe potential reached the range and on return from the digital level adrive strength equal to those driving elements is kept active initially.

Preferably, the drive strength is stepped up to a predetermined levelonce the potential has reached the predetermined range. In this way itis counteracted that the potential can leave the range at the end of thedisturbance that made the potential reach the range too soon, or due toanother disturbance. In this embodiment the drive strength is preferablyswitched back from this predetermined strength to the level representedby the stored information once a signal has been received that commandsthat the potential must be changed away from the predetermined level.

In a further embodiment a counter circuit is used, with a count outputthat controls a number of driving elements that is activated in parallelto drive the potential on the communication conductor. The countercircuit counts up during switching to the digital level and down duringswitching away from the digital level. In this embodiment counting isdisabled in response to detection that the range has been reached andthe counting direction is reversed once the signal has been receivedthat commands that the potential must be changed away from thepredetermined level.

These and other objects and advantageous aspects of the invention willbe illustrated by means of non-limitative examples that are describedusing the following Figures.

FIG. 1 shows an electronic circuit

FIG. 2 shows a signal on a digital communication conductor

FIG. 3 shows a control circuit

FIG. 1 shows an electronic circuit, comprising a digital source circuit10, a driver circuit 12, a bus conductor 14, a pull resistor 16 and adigital receiver circuit 18. Driver circuit 12 comprises a controlcircuit 120, a clock circuit 121, a plurality of current sourcescircuits 122, a plurality of switches 124, and a level detector 126.Each of the current source circuits 122 forms a respective driver branchin series with a respective one of the switches 124. Although only threesuch branches are shown for the sake of clarity, it should be understoodthat a larger number may be present. A plurality of driver branches iscoupled in parallel between bus conductor 14 and a first power supplyconnection V1. Digital source circuit 10 has an output coupled tocontrol circuit 120. Clock circuit 121 is coupled to a clock input ofcontrol circuit 120. Level detector 126 has an input coupled to busconductor 14 and an output coupled to a control input of control circuit120. Control circuit 120 has control outputs coupled to control inputsof switches 124. Bus conductor 14 is coupled to a second power supplyconnection V2 via pull resistor 16. Digital receiver circuit 18 has aninput coupled to bus conductor 14.

FIG. 2 shows signals that illustrate operation of the circuit. Inoperation digital source circuit 10 supplies a binary signal I to drivercircuit 12. In response to a first transition 30 in the binary signaldriver circuit 12 starts pulling a potential B of bus conductor 14 awayfrom a potential of second power supply connection V2, toward apotential of first power supply connection V1. The top of a range ofpotentials wherein level detector 126 detects that the potential B hasreached a required range is indicated by a top level 34; this range mayextend indefinitely to lower levels. In response to a second transition32 (opposite to the first transition) driver circuit 12 starts releasingthe potential B of bus conductor 14, permitting the potential B of busconductor 14 to return towards the potential of the second power supplyconnection V2.

In response to the first transition control circuit 120 controlsswitches 124 to switch on one after the other, so that a progressivelyincreasing number of current source circuits 122 supplies current to busconductor 14. Level detector 126 detects whether the potential B of busconductor 14 has reached a potential range that corresponds to therequired logic level that corresponds to the output signal I of digitalsource circuit 10 (e.g. a range from one volt above the potential ofpower supply conductor V1). Level detector 126 applies a detectionsignal D to control circuit 120, to signal when level detector 126 hasdetected that the potential B of bus conductor 14 has entered thisrange. In response control circuit 120 switches on all switches 124, sothat the potential of bus conductor 14 is subsequently pulled towardsthe potential of first power supply connection V1 with maximum strength.

By way of example, the Figure shows that control circuit 120 has causedthe control signal S1 of one of switches 124 to switch on a switch 124before level detector 126 detected that the potential B of bus conductor14 has entered the required range. Subsequently, control circuit 120causes the control signals S2-Sn of all other switches 124 to switchthese switches on as well. It should be understood that it is merely anexample that only one switch has been switched on before level detector126 detects that the potential B of bus conductor 14 entered therequired range. Dependent on busload and disturbing signals on busconductor 14, control circuit 120 may have switched on any number ofswitches 124 at the time of detection that the potential B of busconductor 14 entered the required range.

One advantageous aspect of the invention is that in this way drivercircuit 12 switches on all switches 124 once the potential B of busconductor 14 has entered the required range, no matter how this rangehas been reached. Driver circuit 12 switches on all switches 124 bothwhen the range is reached due to current from current sources 122 andwhen the range is reached due to external disturbances. In this waydriver reduces the risk that the potential B of bus conductor 14 returnsafterwards if the range is reached due to external disturbances.

Control circuit 120 “remembers” the number of switches 124 that wasswitched on just before level detector 126 signaled that the potentialof bus conductor 14 has entered the required range. However, during thetime interval that digital source circuit 10 signals that potential ofbus conductor 14 has to remain in this range control circuit 120 andafter level detector 126 has detected that the potential B of busconductor 14 has entered the required range control circuit 120 keepsall switches 124 switched-on. That is, typically more switches 124 arekept on than control circuit remembers to have been on just before thepotential of bus conductor 14 entered the required range.

When digital source circuit 10 signals an opposite transition 32,control circuit 120 controls a number of switches 124 to switch offsubstantially simultaneously, so that all but the remembered number ofswitches initially remains switched on after transition 32. The otherswitches are switched off substantially simultaneously in response tothe second transition 32. Subsequently, control circuit 120 switches offthe switches 124 one by one until all switches 124 are switched off.That is, the same number of switched is initially kept switched on asjust before level detector 126 detected that the potential B of busconductor 14 entered the required range. In the Figure, control circuit120 initially switches off all but one of switches 124 after theopposite transition 32 and subsequently control circuit 120 switches offthe remaining switch 124.

In this way the duty cycle (the duration between transitions 30 and 32)is preserved. If disturbance of the potential B of bus conductor 14cause the potential B to reach the required range sooner, then theimmediate switch-off of a number of switches simultaneously,symmetrically with their previous switch-on, causes the potential B toreturn more quickly.

FIG. 3 shows an embodiment of a control circuit 120. The control circuitcontains an up/down Johnson counter 23, a comparator/state register 20,a clock enable circuit 24 and signal selection circuits 26.Comparator/state register 20 has inputs 21, 22 coupled to the output ofdigital source circuit 10 (not shown) and level detector 126 (not shown)respectively. Comparator/state register 20 has an output coupled to anenable input of clock enable circuit 24 and control inputs of signalselection circuits 26. Up/down counter 23 has an up/down control inputcoupled to the output 21 of digital source circuit 10 (not shown).Up/down counter 23 has a clock input coupled to clock circuit 121 (notshown) via clock enable circuit 24. Up/down counter 23 has a rest outputcoupled to comparator/state register 20. Up/down counter 23 has outputscoupled to first inputs of respective ones of signal selection circuits26. Signal selection circuits 26 have second inputs coupled to theoutput 21 of digital source circuit 10 (not shown).

In operation, in a steady state when the output signal of digital sourcecircuit 10 corresponds to the level detected by level detector 126,comparator/state register 20 forces signal selection circuits 26 tooutput a signal corresponding to the signal from digital source circuit10. As a result either none of current source circuit 122 supply currentin the steady state when the output signal of digital source circuit 10is at a first level or all of current source circuit 122 supply currentin the steady state when the output signal of digital source circuit 10is at a second level.

Initially when digital source circuit 10 outputs a signal at a firstlevel and this signal corresponds to the output signal of level detector126 comparator/state register 20 forces signal selection circuits 26 tooutput a signal corresponding to the signal from digital source circuit10. As a result none of current source circuit 122 supplies current tobus conductor 14.

When digital source circuit 10 outputs a transition from the first levelto the second level, comparator/state register 20 detects the resultinglack of correspondence between the output signal of digital sourcecircuit 10 and level detector 126, and switches to a state wherein clockenable circuit 24 passes clock pulses to up/down counter 23 and whereinsignal selection circuits 26 passes output signals from up/down counter23. The signal from digital source circuit 10 causes up/down counter 23to count up in this state. Up/down counter 23 functions as a Johnsoncounter, that is, a counter that raises the signal at an increasingnumber of outputs as more clock pulses are received. At each clock pulseup/down counter 23 outputs control signals to switch on a greater numberof switches 124. Signal selection circuits 26 pass these signals toswitches 124.

When level detector 126 detects a resulting transition of the signal atbus conductor 14, level detector signals this to comparator/stateregister 20. In response comparator/state register 20 resets to thesteady state wherein comparator/state register 20 disables the supply ofclock pulses to up/down counter 23. Furthermore, in this statecomparator/state register 20 forces signal selection circuits 26 tooutput a signal corresponding to the signal from digital source circuit10. As a result all of current source circuit 122 supply current to busconductor 14.

When digital source circuit 10 outputs a transition back from the secondlevel to the first level, comparator/state register 20 detects theresulting lack of correspondence between the output signal of digitalsource circuit 10 and level detector 126, and switches to a statewherein clock enable circuit 24 passes clock pulses to up/down counter23 and wherein signal selection circuits 26 passes output signals fromup/down counter 23. The signal from digital source circuit 10 causesup/down counter 23 to count down in this state. Up/down counter startsfrom the count where it left off after the transition from the firstlevel to the second level. At each clock pulse up/down counter 23outputs control signals to switch on a smaller number of switches 124.Signal selection circuits 26 pas these signals to switches 124.

When the output signal of digital source circuit 10 is at the secondsignal level comparator/state register 20 switches back to the steadystate when up/down counter 23 signals that all switches have beenswitched off. Back in the steady state comparator/state register 20forces signal selection circuits 26 to output a signal corresponding tothe signal from digital source circuit 10. As a result none of currentsource circuit 122 supply current to bus conductor 14.

It should be appreciated that the invention is not limited to theembodiments shown in the Figure. It will be appreciated that many othercircuit implementations exist that are able to produce the same kind ofperformance. It will also be appreciated that many variations arepossible in the circuits that have been shown.

Preferably all current source circuits 122 are designed to deliversubstantially the same current, so that a substantially linear increaseof driving strength can be realized as a function of time. But withoutdeviating from the invention current source circuits 122 may be usedthat produce mutually different driving strength. Current sourcecircuits 122 are preferably realized using high impedance currentsources (realized e.g. by connecting the drains of respective currentsource transistors to bus conductor 14). However, in an alternativeembodiment current source circuits 122 may have lower impedance outputs,using for example resistances as current source circuits 122. Switches124 have been shown il series with current sources 122. These switchescan be realized by means of switch transistors that have their maincurrent channels in series with current source circuits 122, the gateelectrodes of the switch transistors being controlled by control circuit120. However, it will be understood that an equivalent circuit functioncan be realized for example by using switches that short circuit thegate source connection of a current source transistor that performs thecurrent source function and whose drain is connected to bus conductor14.

Instead of a Johnson up/down counter 23 another type of counter may beused, for example a normal counter followed by a decoder circuit thatdecodes a counter value output of the counter to control signals forswitches 124. In fact the state of the counter need not remain stored inthe counter. Instead the count that was reached may be stored elsewhere,for example in a computer memory, and restored when the potential of busconductor 14 must be released. A separate register may be used for thecount and the result may be added to a count value of the counter.

Instead of switching on progressively more switches to increase thecurrent, some switches may be switched off when others are switched onas long as the current is increased, for example when a current sourcethat is switched on in this way is stronger than a current source thatis switched off.

Furthermore, although a single asymmetrically driven bus conductor 14has been shown, it will be understood that in practice more busconductors 14 may be used in parallel, some or all of which may bedriven in a similar way. Also the potential of bus conductor 14 may bedriven in both directions, optionally both with a driver circuit that issimilar to the driver circuit of FIG. 1.

In a further embodiment not all of switches 124 are switched on whenlevel detector 126 indicates that the potential B of bus conductor 14has reached the required range. For example a predetermined fraction ofswitches may be switched on, an excess of switches above that fractionbeing switched on only if the rate of change of the potential B of busconductor 14 is too slow. In another embodiment a predetermined fractionof the switches may be switched off later while digital source circuit10 still indicates that potential B of bus conductor 14 should be pulledaway from the potential of second power supply connection V2.

In yet another embodiment only the number of switches 124 remainsswitched on that were switched on when level detector 126 indicates thatthe potential B of bus conductor 14 has reached the required range. Thishas the disadvantage that too few switches may remain switched on if therange was reached due to external disturbances. But in an embodiment,control circuit 120 may arranged to determine whether the number ofswitches 124 that is switched on is within a predetermined normal rangeof numbers (which indicative of the fact that the required potentialrange was not reached due to disturbances) and if the number is in thenormal range control circuit leaves a number of switches 124 on that wasswitched on when level detector 126 indicates that the potential B ofbus conductor 14 reached the required potential range. Alternativelycontrol circuit 120 may switch on this number of switches 124 plus apredetermined number of additional one of switches 124.

In yet another embodiment a single driver transistor may be used insteadof the plurality of current sources 122. In this case, the controlsignal of this single driver transistor is changed as a function of timewhen the potential B of bus conductor 14 is pulled away from thepotential of second power supply connection V2. A representation of thecontrol signal that was reached is stored in this case. When thepotential B of bus conductor 14 is allowed to return to the potential ofsecond power supply connection V2, this stored value is used to set theinitial control signal value. The control this single driver transistorbeing stepped up or down in the same way as the number of activatedswitches 124 is stepped up or down. However, the use of a single drivertransistor has the disadvantage that its variable control signal is moresusceptible to disturbance than the control signals of switches 124 thatonly have to be switched on and off and need not each be changed in moresteps.

1. An electronic circuit comprising a digital communication conductorand a driver circuit with an output coupled to the digital communicationconductor, for driving changes of a potential at the digitalcommunication conductor to and from a digital signal level, the drivercircuit comprising: a control circuit, arranged to generate selectionsignals that select increasingly stronger drive strengths andincreasingly weaker drive strengths during changes to and from thedigital level respectively; a controllable current supply circuit, witha current control input coupled to the control circuit for receiving theselection signals and a current supply output coupled to the digitalcommunication conductor; a detector circuit with an input coupled to thedigital communication conductor and an output coupled to the controlcircuit, and arranged to detect whether a potential at the digitalcommunication conductor has reached a required range; wherein thecontrol circuit is arranged to store information about the drivestrength that was selected when the detector circuit indicated that therange was reached during the change to the digital level, and to selectthe stored drive strength as a first step during the change away fromthe digital level.
 2. An electronic circuit according to claim 1,wherein the control circuit is arranged to increase the selected drivestrength to a predetermined value upon detection that the range wasreached, and to return the selected drive strength from thepredetermined value to the stored drive strength as the first step ofthe change away from the digital level.
 3. An electronic circuitaccording to claim 1, wherein the adjustable current supply circuitcomprises a plurality of driving elements of predetermined strengthcoupled in parallel to the digital communication conductor, the controlcircuit being arranged to control which of the driving elements will beactive, said information being indicative of a count of number ofdriving elements that were active when the detector circuit indicatedthat the digital level had been detected.
 4. An electronic circuitaccording to claim 3, wherein the control circuit is arranged toactivate an additional number of driving elements in response todetection that the range is reached, so that in total a predeterminednumber of driving elements is activated, and to deactivate saidadditional number of driving elements substantially simultaneously assaid first step.
 5. An electronic circuit according to claim 2, whereinthe control circuit comprises a counter circuit, with a count outputcoupled to control how many of the driving elements are activated inparallel, the counter circuit being arranged to count up duringswitching to the digital level and down during switching away from thedigital level, the control circuit disabling counting in response todetection that the range has been reached.
 6. An electronic circuitaccording to claim 5, wherein the control circuit comprises an overrulecircuit arranged to activate a predetermined number of the drivingelements, irrespective of a count reached by the counter, in response todetection that the range has been reached.
 7. An method of controllingtransitions of a potential on a digital communication conductor to andfrom a digital level, the method comprising: progressively increasing adrive strength when the potential of the communication is changed to thedigital level; detecting whether the potential has reached apredetermined range; storing information about a drive strength that wasused when the predetermined range; restoring the drive strength to thedrive strength represented by the stored information at a start of achange away from the digital level.
 8. A method according to claim 7,wherein the drive strength is stepped up to a predetermined level inresponse to detection that the potential has reached the predeterminedrange.